ss2015 cmos high se nsitivity micropower hall latch 1 v 3 . 10 nov 1 , 20 1 3 packages f eat u r es a n d b e n ef i ts 3 pin sip (suffix ua) 1. operation down to 4 .5v 2. wide operating voltage range 3. high sensitivity for direct reed switch r e- placement applications 4. o utput switches with absolute value of north or south pole from magnet 5. temperature compensation 6. open - collector pre - driver 7. 60v maximum withstand voltage 8. reverse polarity protection 9. package: to - 92s(sip ) functional block diagram application examples 1. brush - less dc motor 2. brush - less dc fan 3. revolution counting 4. speed measurement general description: the ss2015 hall effect latch sensor ic is fabricated fr om mixed signal cmos technology . it incorporates a d- vanced chopper - stabilization techniques to provide accurate and stable magnetic switch points. the circuit design provides an internally controlled clocking mechanism to cycle power to the hall element and analog signal proces sing circuits. this serves to place the high current - consuming portions of the circuit into a ?sleep? mode. periodically the device is ?awakened? by this internal logic and the magnetic flux from the hall element is evaluated a gainst the predefined thresho lds. if the flux density is above or below the b op /b rp thres h- olds then the output transistor is driven to change states accordingly. while in the ?sleep? cycle t he output tra n- sistor is latched in its previous state. the design has been optimized for service in applications requiring extended operating lifetime in battery powered systems. an internal bandgap regulator is used to provide temperature co m- pensated supply voltage for internal circuits and allows a wide operating supply range. the output tra nsistor of the ss2015 will be latched on (b op ) in the presence of a sufficiently strong south or north magnetic field facing the marked side of the package. the output will be latched off (b rp ) in the absence of a magnetic field. 3 pin sot23w (suffix so )
ss2015 cmos high se nsitivity micropower hall latch 2 v 3 . 10 nov 1 , 20 1 3 typical application cir cuit sec 's pole - independent sensing technique allows for operation with either a north pole or south pole magnet orientation, enhancing the manufacturability of the device. the state - of - the - art technology provides the same output polarity for either pole face. it is strongly recommended that an external bypass be connected (in close proximity to the hall sensor) between the supply and ground of the device to reduce both external n oise and noise generated by the cho p- per - stabilizatio n technique. this is especially true due to the relatively high impedance of battery supplies. functional block diagrams voltage hall plate amp v dd gnd output
ss2015 cmos high se nsitivity micropower hall latch 3 v 3 . 10 nov 1 , 20 1 3 pin definitions and descriptions sip pin name type function 1 v dd supply supply voltage pin 3 out output open drain output pin 2 gnd ground ground pin absolute maximum ratings parameter symbol value units supply voltage (operating) v dd 24 v reverse voltage, - v dd - 24 v output voltage v out 30 v output current i out 5 0 ma operating temperature range t a - 2 0 to 85 c storage temperature range t s - 55 to 1 50 c esd sensitivity - 4000 v exceeding the absolute maximum ratings may cause permanent damage. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. dc electrical characteristic s dc operating parameters : t a = 25 c , v dd = 12 v . parameter symbol test conditions min typ max units operating voltage v dd operating 4 .5 5 24 v supply current i dd average 5 10 m a saturation voltage v sat i out = 20 ma , b>b op 0.4 0. 5 v output leakage i off b ss2015 cmos high se nsitivity micropower hall latch 4 v 3 . 10 nov 1 , 20 1 3 magnetic characteristic s operating parameters : t a = 25 c , v dd = 12v parameter symbol min typ e max units operating point b op 5 70 g s release point b rp - 70 - 5 g s hysteresis b hys t 80 g s esd protection human body model (hbm) tests according to: mil. std. 883f method 3015.7 parameter symbol limit values unit notes min max esd voltage v esd 4 kv performance characteristics unique features cmos hall ic technology the chopper stabilized amplifier uses switched capacitor techniques to eliminate the amplifier offset voltage, which, in bipolar devices, is a major source of temperature sensitive drift. cmos makes this advanced technique possible. the cmos chip is also much smaller than a bipolar chip, allowing very sophisticated circuitry to be placed in less space. the small chip size also contributes to lower physical stress and less power consumption. installation c omments consider temperature coefficients of hall ic and magnetic , as well as air gap and life time variations. observe temperature limits during wave soldering. typical ir solder - reflow profile: ? no rapid heating and cooling. ? recommended preheating for max. 2minutes at 150c ? recommended reflowing for max. 5seconds at 240 c
ss2015 cmos high se nsitivity micropower hall latch 5 v 3 . 10 nov 1 , 20 1 3 esd precautions electronic semiconductor products are sensitive to electro static discharge (esd). always observe electro static discharge control procedures whenever handling semiconductor products.
ss2015 cmos high se nsitivity micropower hall latch 6 v 3 . 10 nov 1 , 20 1 3 package information package ua, 3 - pin ip: ordering information part no. pb - free temperature code package code packing ss2015 eua yes - 40c to 85c t o - 92 bulk, 1 000 pieces/ bag ss2015 kua yes - 40c to 12 5c t o - 92 bulk, 1 000 pieces/ bag ss2015 l ua yes - 40c to 150 c t o - 92 bulk, 1 000 pieces/ bag 4.0 0.01 1 2 3 1.27 2.13 1.87 1.00 1.20 45 1 1.52 0.1 3 1 0.75 0.05 3.0 0.01 0.44 0.01 0.05 0.05 1.6. 0.1 0.84(nom) 3 1 6 1 6 1 3 1 14 .5 1 active area depth: sensor location 1 2 3 notes: 1). controlling dimension : mm ; 2). le a ds must be free of flash and plating voids ; 3). do not bend leads within 1 mm of lead to package interface ; 4). pinout: pin 1 v dd pin 2 gnd pin 3 output 0.39 0.01 0.38 0.01 2.54
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